Furthermore, this is the maximum throughput that is available to the entire ADC device, so if you're using more than one channel on the ADC, this 250 kHz would have to be split between the channels you're using.Previous Section Next Section INTRODUCTION
Thus, the processor is the limiting factor here it can only support a maximum of a 250 kHz sample rate. It is stated elsewhere in the datasheet that a "CPU clock period" as referenced here is equivalent to $\frac This means that the minimum SCK period will be two CPU clock periods. When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 18-5 Specifically, look at the bottom of page 166: #1 is dictated by the capabilities of your host processor, and can be found in the datasheet. #2 in the above list is very clearly stated to be 1 MHz. The maximum conversion rate that the ADC supports.The SPI clock rate (as it determines how long it takes to extract 16 bits).In the above timeline, the speed of the conversion is therefore limited by two factors: The master deasserts the CS pin to end the transaction.After that, the master has received 16 serial bits from the ADC, which contain the conversion result. For this ADC device, the transaction continues for 16 bits.This is used to simultaneously shift data in and out of the ADC serially. The SPI master begins to apply a clock signal to the ADC on the SCLK pin.From the ADC's perspective, this would be the DIN pin. If the SPI master has any data to write to the device, it presents it in serial fashion on the MOSI (master out, slave in) signal.the host processor) asserts the CS signal. The mechanics of an SPI read go like this: That signal is asserted each time the host processor initiates a transaction to the converter. There are no pipeline delays associated with the part.ĬS in this case refers to the chip select pin on the ADC's SPI-compatible 4-wire serial bus. The input signal is sampled on the falling edge of CS and conversion is initiated at this point. The conversion process and data acquisition are controlled usingĬS and the serial clock signal, allowing the device to easily interface Look at the second paragraph of the General Description on the first page of the ADC datasheet: This question isn't particularly on-topic, but the answer is pretty simple.
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